Hi.

It seems, that sometimes data in cached memory is corrupted.

DMA transfer data from SPI to SRAM2 (0x30000000). I use ping-pong buffer in SRAM2 (two similar buffers). Data processing performing for first part of the buffer in thread, while second it's part is filled with data over DMA.

 DMA write 35 bytes to buffer. DMA start next time and write to next 35 bytes and so on 72 times. After 35*72 bytes are written into first part of the ping-pong buffer, it swap to second part. Both parts are 35*72 bytes.

 Both start address of buffer parts are alligned to 32 bytes (but size of buffer is not alligned to 32 and accsess from thread is one byte alligned).

Of course invalidate cache before processing is performed. Buffer part for thread (35*72 bytes) is invalidated. But sometimes data in buffer seems is not valid.

 Usually failed data that correspond one DMA transaction (all 35 bytes), but one or some corrupted bytes meet too.

When cache is disabled there is no one error for very long period of time. When cache is enabled error rates is about 1e-6. It is too much for my application.

Additional considerations

Do you have any suggestions?

Regards, Aleks.

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